Device test times also are rising dramatically. Longer test times are driven by higher levels of embedded memory, higher functionality, higher quality requirements, and the need to move more tests to ...

The high costs of building, resourcing and operating a foundry fabricating integrated circuits are well known. Fabless companies avoid this capital cost and focus on design and innovation in their ...

Test strategy analysis has become increasingly important for finding ways to reduce test costs for system-on-a-chip (SoC) semiconductor devices. Every SoC device’s test flow is unique and requires a ...

SANTA CLARA, Calif.–Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its “casual learning algorithm” technology for wafer sort applications in the fab. Intel is looking to ...

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming ...