Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...

Cadence Design Systems stock was climbing as it said its AI agent can now independently carry out complex work on chip design ...

It’s often said that “the secret to a good marriage is good communication” but it’s equally true that good communication is the secret to a successful IP or system-on-chip (SoC) project. Such projects ...

Cadence unveiled a Level-5 autonomous AI design engineer powered by NVIDIA technologies, aiming to reduce semiconductor ...

A key Cadence differentiator is that autonomous agent behavior is tightly coupled with the company’s core physics-based design and verification engines. This keeps AI-directed actions grounded in ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...